There is an increasing demand for digital integrated circuits to operate at higher speeds while minimizing power consumption. To achieve the desired balance between power consumption and performance across a wide variety of applications and operation conditions, digital integrated circuits are sometimes provided with dynamic voltage-frequency scaling (DVFS) capabilities.
In a conventional dynamic voltage-frequency scaling scheme, an integrated circuit is able to operate at different voltage-frequency points. When higher performance is needed, the voltage can be increased to reduce gate delays and to allow for an increase in clocking frequency. When low power consumption is desired, the clocking frequency is decreased to allow for a reduction in voltage. The integrated circuit may be placed in these different voltage-frequency states depending on changes in current incoming workload or operation conditions.
Conventional DVFS schemes allow integrated circuits to operate at discrete voltage-frequency points or over a continuous voltage-frequency range. The relationship between the voltage and frequency is, however, fixed at design time and is determined by the particular circuit structure. For example, consider a scenario in which an integrated circuit includes combinational logic that is interposed between two flip-flop circuits, where the combinational logic exhibits a propagation delay of four nanoseconds when the combinational logic is powered using a supply voltage of 1.0 V. In this example, the maximum operating frequency at which the flip-flop circuits could be operated is limited to 250 MHz. In other words, the maximum operating frequency at a given voltage is determined entirely by the circuit structure of the combinational logic and, more particularly, by the delay associated with the combinational logic, neither of which can be adjusted after fabrication.